The invention relates generally to semiconductor devices and integrated circuit fabrication and, in particular, to structures for field-effect transistors and methods for fabricating a structure for field-effect transistors.
Device structures for a field-effect transistor generally include a source, a drain, and a gate electrode configured to switch carrier flow between the source and drain in a channel formed in an active region of semiconductor material arranged beneath the gate electrode. When a control voltage exceeding a designated threshold voltage is applied to the gate electrode, the flow of carriers in the channel produces a device output current.
The source and drain are directly contacted from above by a contact structure that includes a trench silicide contact and a metal contact that connects the trench silicide contact with a track among a set of parallel tracks in an overlying metallization level. The metal contact has a resistance that scales inversely with area. As the track pitch scales downward and the available space for the metal contact decreases, the related reduction in area of the metal contact may increase the resistance to an unacceptable value. The spacing between the tracks in the overlying metallization level also decreases with decreasing track pitch. As a result of tighter spacing, the metal contact cannot be arbitrarily widened without a risk of shorting to a neighboring track that is arranged adjacent to the contacted track. This restriction may also prohibit contacting a track that is not arranged over the active region.
Improved structures for field-effect transistors and methods for fabricating a structure for field-effect transistors are needed.